1. Technical Field
The present disclosure relates to test a layout of signal lines, and particularly relates to a computing device and a method for testing a layout of power pins of chipsets on a circuit board.
2. Description of Related Art
A printed circuit board mechanically supports and electrically connects electronic components thereon. Power pins of the electronic components are supplied with a steady direct current (DC) power, such as 5V, 3V, 1.8V, and so on. The power pins are usually connected to a power source layer of the printed circuit board. However, the power source layer is located in an interior of the printed circuit board, and the electronic components are usually mounted on an outer surface of the printed circuit board. Therefore, a plurality of vias are defined in the printed circuit board to connect the power pins to the power source layer. However, if a transmission line between the power pin and the via is too long, a strong inference signal will be generated, which interferes with power supplied to the electronic component. Thus, a layout of the printed circuit board needs to be tested. However, existing testing technology depends heavily on human experience and judgment, which results in a low accuracy and a low efficiency.